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| (R) 74LVQ273 OCTAL D-TYPE FLIP FLOP WITH CLEAR s s s s s s s s s s s HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUT LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.4 V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ273M 74LVQ273T Information signals applied to D inputs are transfered to the Q outputs on the positive going edge of the clock pulse. When the CLEAR inputs is held low, the Q outputs are held low independentely of the other inputs . It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The LVQ273 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/10 74LVQ273 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 SYMBOL CLEAR Q0 to Q7 NAME AND FUNCT ION Asyncronous Master Reset (Active LOW) Flip-Flop Outputs D0 to D7 Data Inputs CLOCK Clock Input (LOW-to-HIGH, EdgeTriggered) Ground (0V) Positive Supply Voltage 10 20 GND VCC TRUTH TABLE INPUTS CL EAR L H H H X:Don't Care OUT PUT S CLO CK X Q L L H Qn F UNCTIO N CLEAR D X L H X NO CHANGE LOGIC DIAGRAM Thislogic diagram has notbe used to esimate propagation delays 2/10 74LVQ273 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 400 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) Parameter Supply Voltage (note 1) Valu e 2 to 3.6 0 to VCC 0 to VCC -40 to +85 0 to 10 Unit V V V o C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 3/10 74LVQ273 DC SPECIFICATIONS Symb ol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 3.0 to 3.6 3.0 VI = V IH or V IL VI(*) = VIH or VIL (* ) Test Co nditions Min. 2.0 T yp. Valu e T A = 25 oC Max. 0.8 -40 to 85 o C Min. 2.0 0.8 2.9 2.48 2.2 0.002 0 0.1 0.36 0.1 4 36 -25 0.1 0.44 0.55 1 40 2.99 Max. Un it V V V I O =-50 A IO=-12 mA IO=-24 mA IO=50 A IO=12 mA IO=24 mA 2.9 2.58 VOL 3.0 V A A mA mA II ICC IOLD IOHD 3.6 3.6 3.6 VI = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min 1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 . (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 3.3 -0.8 3.3 3.3 C L = 50 pF 0.8 Test Co nditions Min. T yp. 0.4 -0.5 2 V Valu e T A = 25 oC Max. 0.8 -40 to 85 o C Min. Max. Un it 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 4/10 74LVQ273 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf =3 ns) Symb ol Parameter V CC (V) tPLH tPHL tPHL tw(L) tw tsL tsH thL thH tREM fMAX tOSLH tOSHL Propagation Delay Time CK to Q Propagation Delay Time CLR to Q CLR pulse Width, LOW CK pulse Width Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Recovery Time CLR to CK Maximum Clock Frequency Output to Output Skew Time (note 1, 2) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3 (*) (*) T est Con ditio n Valu e T A = 25 oC -40 to Min. T yp. Max. Min. 7.5 17.0 6.0 12.0 10.0 9.0 2.5 2.0 2.0 1.5 -0.4 -0.3 0.4 0.3 -0.1 0.0 60 90 150 190 0.5 0.5 1.0 1.0 18.0 13.0 7.0 5.5 7.0 5.5 6.5 5.0 3.0 2.0 5.0 4.0 50 70 Un it 85 o C Max. 20.0 14.0 20.0 14.0 8.5 6.0 8.5 6.0 8.5 6.0 3.5 2.5 6.5 4.5 ns ns ns ns ns ns ns MHz 2.7 3.3(*) 1.5 1.5 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter V CC (V) C IN CPD Input Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 fIN = 10 MHz Test Co nditions Min. T yp. 5 30 Valu e T A = 25 oC Max. -40 to 85 o C Min. Max. pF pF Un it 1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/8(per FlipFlop) 5/10 74LVQ273 TEST CIRCUIT CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500 orequivalent RT = ZOUT of pulse generator (typically 50) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES, CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle) 6/10 74LVQ273 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 3: RECOVERY TIME, CLEAR PULSE WIDTH (f=1MHz; 50% duty cycle) 7/10 74LVQ273 SO-20 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012 P013L 8/10 74LVQ273 TSSOP20 MECHANICAL DATA mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 6.4 6.25 4.3 6.5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.2 6.6 6.5 4.48 0.002 0.335 0.0075 0.0035 0.252 0.246 0.169 0.256 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.260 0.256 0.176 DIM. A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 9/10 74LVQ273 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com . 10/10 |
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